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H8/3028F 数据表(PDF) 290 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 290 Page - Renesas Technology Corp |
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290 / 923 page ![]() Rev. 2.00, 09/03, page 260 of 890 8.5.2 Register Descriptions Table 8.6 summarizes the registers of port 4. Table 8.6 Port 4 Registers Address* Name Abbreviation R/W Initial Value H'EE003 Port 4 data direction register P4DDR W H'00 H'FFFD3 Port 4 data register P4DR R/W H'00 H'EE03E Port 4 input pull-up control register P4PCR R/W H'00 Note: * Lower 20 bits of the address in advanced mode. Port 4 Data Direction Register (P4DDR): P4DDR is an 8-bit write-only register that can select input or output for each pin in port 4. Bit Initial value Read/Write 7 P4 DDR 0 W Port 4 data direction 7 to 0 These bits select input or output for port 4 pins 7 6 P4 DDR 0 W 6 5 P4 DDR 0 W 5 4 P4 DDR 0 W 4 3 P4 DDR 0 W 3 2 P4 DDR 0 W 2 1 P4 DDR 0 W 1 0 P4 DDR 0 W 0 Modes 1 to 5 (Expanded Modes): When all areas are designated as 8-bit-access areas by the bus controller’s bus width control register (ABWCR), selecting 8-bit bus mode, port 4 functions as an input/output port. In this case, a pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0. When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4 functions as part of the data bus, regardless of the P4DDR settings. Modes 6 and 7 (Single-Chip Mode): Port 4 functions as an input/output port. A pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0. P4DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. ABWCR and P4DDR are not initialized in software standby mode. Therefore, if a transition is made to software standby mode while port 4 is functioning as an input/output port and a P4DDR bit is set to 1, the corresponding pin maintains its output state. |
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