AD9520-2SLASHPCBZ datasheet(39/84 Pages) AD

39 / 84 page

AD9520-2

Rev. 0 | Page 39 of 84

External VCXO/VCO Clock Input (CLK/CLK)

External/Manual Holdover Mode

A manual holdover mode can be enabled that allows the user to

place the charge pump into a high impedance state when the

SYNC pin is asserted low. This operation is edge sensitive, not

level sensitive. The charge pump enters a high impedance state

immediately. To take the charge pump out of a high impedance

state, take the SYNC pin high. The charge pump then leaves the

high impedance state synchronously with the next PFD rising

edge from the reference clock. This prevents extraneous charge

pump events from occurring during the time between SYNC

going high and the next PFD event. This also means that the

charge pump stays in a high impedance state if there is no

reference clock present.

This differential input is used to drive the AD9520 clock

distribution section. This input can receive up to 2.4 GHz.

The pins are internally self-biased, and the input signal should

be ac-coupled via capacitors.

CLOCK INPUT

STAGE

CLK

5kΩ

2.5kΩ

The B counter (in the N divider) is reset synchronously with the

charge pump, leaving the high impedance state on the reference

path PFD event. This helps align the edges out of the R and N

dividers for faster settling of the PLL. Because the prescaler is

not reset, this feature works best when the B and R numbers are

close because this results in a smaller phase difference for the

loop to settle out.

Figure 45. CLK Equivalent Input Circuit

The CLK/CLK input can be used either as a distribution only

input (with the PLL off) or as a feedback input for an external

VCO/VCXO using the internal PLL when the internal VCO is

not used. These inputs are also used as a feedback path for the

external zero delay mode.

When using this mode, the channel dividers should be set to ignore

the SYNC pin (at least after an initial SYNC event). If the dividers

are not set to ignore the SYNC pin, any time SYNC is taken low

to put the part into holdover, the distribution outputs turn off.

The channel divider ignore SYNC function is found in 0x191[6],

0x194[6], 0x197[6], and 0x19A[6] for Channel Divider 0, Channel

Divider 1, Channel Divider 2, and Channel Divider 3, respectively.

Holdover

The AD9520 PLL has a holdover function. Holdover is

implemented by placing the charge pump in a high impedance

state. This function is useful when the PLL reference clock is

lost. Holdover mode allows the VCO to maintain a relatively

constant frequency even though there is no reference clock.

Without this function, the charge pump is placed into a constant

pump-up or pump-down state, resulting in a massive VCO

frequency shift. Because the charge pump is placed in a high

impedance state, any leakage that occurs at the charge pump

output or the VCO tuning node causes a drift of the VCO

frequency. This can be mitigated by using a loop filter that

contains a large capacitive component because this drift is

limited by the current leakage induced slew rate (ILEAK/C) of

the VCO control voltage.

Automatic/Internal Holdover Mode

When enabled, this function automatically puts the charge

pump into a high impedance state when the loop loses lock.

The assumption is that the only reason the loop loses lock is due

to the PLL losing the reference clock; therefore, the holdover

function puts the charge pump into a high impedance state to

maintain the VCO frequency as close as possible to the original

frequency before the reference clock disappeared.

Both a manual holdover mode, using the SYNC pin, and an

automatic holdover mode are provided. To use either function, the

holdover function must be enabled (0x01D[0]).

A flowchart of the automatic/internal holdover function

operation is shown in Figure 46.

AD9520-2/PCBZ 数据表(PDF) 39 Page - Analog Devices

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