AD9520-2SLASHPCBZ datasheet(82/84 Pages) AD

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AD9520-2

Rev. 0 | Page 82 of 84

APPLICATIONS INFORMATION

FREQUENCY PLANNING USING THE AD9520

The AD9520 is a highly flexible PLL. When choosing the PLL

settings and version of the AD9520, the following guidelines

should be kept in mind.

The AD9520 has four frequency dividers: the reference (or R)

divider, the feedback (or N) divider, the VCO divider, and the

channel divider. When trying to achieve a particularly difficult

frequency divide ratio requiring a large amount of frequency

division, some of the frequency division can be done by either

the VCO divider or the channel divider, thus allowing a higher

phase detector frequency and more flexibility in choosing the

loop bandwidth.

Within the AD9520 family, lower VCO frequencies generally

result in slightly better jitter. The difference in integrated jitter

(from 12 kHz to 20 MHz offset) for the same output frequency is

usually less than 150 fs over the entire VCO frequency range

(1.4 GHz to 2.95 GHz) of the AD9520 family. If the desired

frequency plan can be achieved with a version of the AD9520

that has a lower VCO frequency, choosing the lower frequency

part results in the best phase noise and the lowest jitter. However,

choosing a higher VCO frequency can result in more flexibility

in frequency planning.

Choosing a nominal charge pump current in the middle of the

allowable range as a starting point allows the designer to increase or

decrease the charge pump current and, thus, allows the designer

to fine-tune the PLL loop bandwidth in either direction.

ADIsimCLK is a powerful PLL modeling tool that can be

downloaded from www.analog.com and is a very accurate tool

for determining the optimal loop filter for a given application.

USING THE AD9520 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Any high speed ADC is extremely sensitive to the quality of the

sampling clock of the AD9520. An ADC can be thought of as a

sampling mixer, and any noise, distortion, or time jitter on the

clock is combined with the desired signal at the analog-to-

digital output. Clock integrity requirements scale with the analog

input frequency and resolution, with higher analog input

frequency applications at ≥14-bit resolution being the most

stringent. The theoretical SNR of an ADC is limited by the ADC

resolution and the jitter on the sampling clock. Considering an

ideal ADC of infinite resolution where the step size and

quantization error can be ignored, the available SNR can be

expressed approximately by

⎟

⎠

⎞

⎜

⎝

⎛

SNR

log

(dB)

where:

fA is the highest analog frequency being digitized.

tJ is the rms jitter on the sampling clock.

Figure 69 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

fA (MHz)

100

110

= 100f

= 200f

= 400f

= 1ps

= 2ps

= 10p

SNR = 20log

2πfAtJ

Figure 69. SNR and ENOB vs. Analog Input Frequency

See the AN-756 Application Note and the AN-501 Application

Note at www.analog.com.

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. Distributing a single-ended clock on a noisy PCB

can result in coupled noise on the sampling clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.

The differential LVPECL outputs of the AD9520 enable clock

solutions that maximize converter SNR performance.

The input requirements of the ADC (differential or single-

ended, logic level termination) should be considered when

selecting the best clocking/converter solution.

LVPECL CLOCK DISTRIBUTION

The LVPECL outputs of the AD9520 provide the lowest jitter

clock signals available from the AD9520. The LVPECL outputs

(because they are open emitter) require a dc termination to bias

the output transistors. The simplified equivalent circuit in

Figure 53 shows the LVPECL output stage.

In most applications, a LVPECL far-end Thevenin termination

(see Figure 70) or Y-termination (see Figure 71) is recommended.

In both cases, VS of the receiving buffer should match the VS_DRV.

If not, ac coupling is recommended (see Figure 72).

LVPECL Y-termination is an elegant termination scheme that

uses the fewest components and offers both odd- and even-mode

impedance matching. Even-mode impedance matching is an

important consideration for closely coupled transmission lines

at high frequencies. Its main drawback is that it offers limited

flexibility for varying the drive strength of the emitter-follower

LVPECL driver. This can be an important consideration when

driving long trace lengths but is usually not an issue. In the case

where VS_DRV = 2.5 V, the 50 Ω termination resistor connected to

ground in Figure 71 should be changed to 19 Ω.

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