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AD9520-2/PCBZ 数据表(PDF) 79 Page - Analog Devices |
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AD9520-2/PCBZ 数据表(HTML) 79 Page - Analog Devices |
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79 / 84 page ![]() AD9520-2 Rev. 0 | Page 79 of 84 Reg. Addr (Hex) Bit(s) Name Description 19B [1] Channel 3 direct-to-output Connects OUT9, OUT10, and OUT11 to Divider 3 or directly to VCO or CLK. [1] = 0; OUT9, OUT10, and OUT11 are connected to Divider 3 (default). [1] = 1: If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT9, OUT10, and OUT11. If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT9, OUT10, and OUT11. If 0x1E1[1:0] = 01b, there is no effect. 19B [0] Disable Divider 3 DCC Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. Table 56. VCO Divider and CLK Input Reg. Addr (Hex) Bit(s) Name Description 1E0 [2:0] VCO divider [2] [1] [0] Divide 0 0 0 2 (default) 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 Output static 1 1 0 1 (bypass) 1 1 1 Output static 1E1 [4] Power-down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree). [4] = 0; normal operation (default). [4] = 1; power down. 1E1 [3] Power-down VCO clock interface Powers down the interface block between VCO and clock distribution. [3] = 0; normal operation (default). [3] = 1; power down. 1E1 [2] Power-down VCO and CLK Powers down both the CLK input and the VCO. [2] = 0; normal operation (default). [2] = 1; power down. 1E1 [1] Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider. [1] = 0; select external CLK as input to VCO divider (default). [1] = 1; select VCO as input to VCO divider; cannot bypass VCO divider when this is selected. This bit must be set to use the PLL with the internal VCO. 1E1 [0] Bypass VCO divider Bypasses or uses the VCO divider. [0] = 0; use VCO divider (default). [0] = 1; bypass VCO divider; cannot select VCO as input when this is selected. |
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