AD9520-2SLASHPCBZ datasheet(83/84 Pages) AD

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AD9520-2

Rev. 0 | Page 83 of 84

Thevenin-equivalent termination uses a resistor network to

provide 50 Ω termination to a dc voltage that is below VOL of

the LVPECL driver. In this case, VS_DRV on the AD9520

should equal VS of the receiving buffer. Although the resistor

combination shown results in a dc bias point of VS_DRV − 2 V,

the actual common-mode voltage is VS_DRV − 1.3 V because

there is additional current flowing from the AD9520 LVPECL

driver through the pull-down resistor.

The circuit is identical for the case where VS_DRV = 2.5 V, except

that the pull-down resistor is 62.5 Ω and the pull-up is 250 Ω.

VS_DRV

LVPECL

50Ω

SINGLE-ENDED

(NOT COUPLED)

VS_DRV

LVPECL

127Ω

83Ω

Figure 70. DC-Coupled 3.3V LVPECL Far-End Thevenin Termination

VS_DRV

LVPECL

Z0 = 50Ω

VS = VS_DRV

LVPECL

50Ω

Z0 = 50Ω

Figure 71. DC-Coupled 3.3 V LVPECL Y-Termination

VS_DRV

LVPECL

100Ω DIFFERENTIAL

(COUPLED)

TRANSMISSION LINE

LVPECL

100Ω

0.1nF

200Ω

Figure 72. AC-Coupled LVPECL with Parallel Transmission Line

CMOS CLOCK DISTRIBUTION

The output drivers of the AD9520 can be configured as CMOS

drivers. When selected as a CMOS driver, each output becomes

a pair of CMOS outputs, each of which can be individually

turned on or off and set as inverting or noninverting. These

outputs are 3.3 V or 2.5 V CMOS compatible. However, every

output driver (including the LVPECL drivers) must be run at

either 2.5 V or 3.3 V. The user cannot mix and match 2.5 V and

3.3 V outputs.

When single-ended CMOS clocking is used, some of the

following guidelines apply.

Point-to-point connections should be designed such that each

driver has only one receiver, if possible. Connecting outputs in

this manner allows for simple termination schemes and minimizes

ringing due to possible mismatched impedances on the output

trace. Series termination at the source is generally required to

provide transmission line matching and/or to reduce current

transients at the driver.

The value of the resistor is dependent on the board design and

timing requirements (typically 10 Ω to 100 Ω is used). CMOS

outputs are also limited in terms of the capacitive load or trace

length that they can drive. Typically, trace lengths less than

3 inches are recommended to preserve signal rise/fall times and

signal integrity.

CMOS

10Ω

60.4Ω

(1.0 INCH)

MICROSTRIP

Figure 73. Series Termination of CMOS Output

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the AD9520 do not supply enough current

to provide a full voltage swing with a low impedance resistive, far-

end termination, as shown in Figure 74. The far-end termination

network should match the PCB trace impedance and provide the

desired switching point. The reduced signal swing may still meet

receiver input requirements in some applications. This can be

useful when driving long trace lengths on less critical nets.

CMOS

10Ω

50Ω

100Ω

Figure 74. CMOS Output with Far-End Termination

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The AD9520 offers LVPECL outputs

that are better suited for driving long traces where the inherent

noise immunity of differential signaling provides superior

performance for clocking converters.

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