AD9520-2SLASHPCBZ datasheet(16/84 Pages) AD

16 / 84 page

AD9520-2

Rev. 0 | Page 16 of 84

POWER DISSIPATION

Table 18.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER DISSIPATION, CHIP

Does not include power dissipated in external resistors; all

LVPECL outputs terminated with 50 Ω to VCC − 2 V; all CMOS

outputs have 10 pF capacitive loading; VS_DRV = 3.3 V

Power-On Default

1.32

1.5

No clock; no programming; default register values

PLL Locked; One LVPECL Output Enabled

0.55

0.64

fREF = 25 MHz; fOUT = 250 MHz; VCO = 2250 MHz; VCO divider = 2;

one LVPECL output and output divider enabled; zero delay off;

ICP = 4.8 mA

PLL Locked; One CMOS Output Enabled

0.52

0.62

fREF = 25 MHz; fOUT = 62.5 MHz; VCO = 2250 MHz; VCO divider = 2;

one CMOS output and output divider enabled; zero delay off;

ICP = 4.8 mA

Distribution Only Mode; VCO Divider On;

One LVPECL Output Enabled

0.39

0.46

fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider = 2;

one LVPECL output and output divider enabled; zero delay off

Distribution Only Mode; VCO Divider Off;

One LVPECL Output Enabled

0.36

0.42

fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider bypassed;

one LVPECL output and output divider enabled; zero delay off

Maximum Power, Full Operation

1.5

1.7

PLL on; internal VCO = 2250 MHz; VCO divider = 2; all channel

dividers on; 12 LVPECL outputs @ 125 MHz; zero delay on

PD Power-Down

PD pin pulled low; does not include power dissipated

in termination resistors

PD Power-Down, Maximum Sleep

PD pin pulled low; PLL power-down, 0x010[1:0] = 01b; power-

down SYNC, 0x230[2] = 1b; power-down distribution reference,

0x230[1] = 1b

VCP Supply

4.8

PLL operating; typical closed-loop configuration

POWER DELTAS, INDIVIDUAL FUNCTIONS

Power delta when a function is enabled/disabled

VCO Divider On/Off

VCO divider not used

REFIN (Differential) Off

Delta between reference input off and differential reference

input mode

REF1, REF2 (Single-Ended) On/Off

Delta between reference inputs off and one singled-ended

reference enabled; double this number if both REF1 and REF2

are powered up

VCO On/Off

104

Internal VCO disabled; CLK input selected

PLL Dividers and Phase Detector On/Off

PLL off to PLL on, normal operation; no reference enabled

LVPECL Channel

121

144

No LVPECL output on to one LVPECL output on; channel divider

set to 1

LVPECL Driver

Second LVPECL output turned on, same channel

CMOS Channel

145

180

No CMOS output on to one CMOS output on; channel divider

set to 1; fOUT = 62.5 MHz and 10 pF of capacitive loading

CMOS Driver On/Off

Additional CMOS outputs within the same channel turned on

Channel Divider Enabled

Delta between divider bypassed (divide-by-1) and divide-by-2 to

divide-by-32

Zero Delay Block On/Off

AD9520-2/PCBZ 数据表(PDF) 16 Page - Analog Devices

AD9520-2/PCBZ 数据表(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

数据表下载