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AD9520-2/PCBZ 数据表(PDF) 10 Page - Analog Devices |
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AD9520-2/PCBZ 数据表(HTML) 10 Page - Analog Devices |
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10 / 84 page  AD9520-2 Rev. 0 | Page 10 of 84 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter Min Typ Max Unit Test Conditions/Comments CLK-TO-LVPECL ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 1 GHz Input slew rate > 1 V/ns Divider = 1 @ 10 Hz Offset −107 dBc/Hz @ 100 Hz Offset −117 dBc/Hz @ 1 kHz Offset −127 dBc/Hz @ 10 kHz Offset −135 dBc/Hz @ 100 kHz Offset −142 dBc/Hz @ 1 MHz Offset −145 dBc/Hz @ 10 MHz Offset −147 dBc/Hz @ 100 MHz Offset −150 dBc/Hz CLK = 1 GHz, Output = 200 MHz Input slew rate > 1 V/ns Divider = 5 @ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −143 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −156 dBc/Hz @ 1 MHz Offset −157 dBc/Hz >10 MHz Offset −157 dBc/Hz CLK-TO-CMOS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 250 MHz Input slew rate > 1 V/ns Divider = 4 @ 10 Hz Offset −107 dBc/Hz @ 100 Hz Offset −119 dBc/Hz @ 1 kHz Offset −125 dBc/Hz @ 10 kHz Offset −134 dBc/Hz @ 100 kHz Offset −144 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −154 dBc/Hz CLK = 1 GHz, Output = 50 MHz Input slew rate > 1 V/ns Divider = 20 @ 10 Hz Offset −126 dBc/Hz @ 100 Hz Offset −133 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −148 dBc/Hz @ 100 kHz Offset −157 dBc/Hz @ 1 MHz Offset −160 dBc/Hz >10 MHz Offset −163 dBc/Hz |
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