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AD9520-2/PCBZ 数据表(PDF) 13 Page - Analog Devices |
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AD9520-2/PCBZ 数据表(HTML) 13 Page - Analog Devices |
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13 / 84 page  AD9520-2 Rev. 0 | Page 13 of 84 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 12. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz; Channel Divider = 2; Duty-Cycle Correction = Off 230 fs rms Calculated from SNR of ADC method (broadband jitter) CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = On 215 fs rms Calculated from SNR of ADC method (broadband jitter) CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = Off 326 fs rms Calculated from SNR of ADC method (broadband jitter) CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz; Channel Divider = 8; Duty-Cycle Correction = Off 362 fs rms Calculated from SNR of ADC method (broadband jitter) SERIAL CONTROL PORT—SPI MODE Table 13. Parameter Min Typ Max Unit Test Conditions/Comments CS (INPUT) CS has an internal 30 kΩ pull-up resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 μA Input Logic 0 Current −110 μA The minus sign indicates that current is flowing out of the AD9520, which is due to the internal pull-up resistor Input Capacitance 2 pF SCLK (INPUT) IN SPI MODE SCLK has an internal 30 kΩ pull-down resistor in SPI mode, but not in I2C mode Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF SDIO (WHEN AN INPUT IN BIDIRECTIONAL MODE) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 1 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V TIMING Clock Rate (SCLK, 1/tSCLK) 25 MHz Pulse Width High, tHIGH 16 ns Pulse Width Low, tLOW 16 ns SDIO to SCLK Setup, tDS 4 ns SCLK to SDIO Hold, tDH 0 ns SCLK to Valid SDIO and SDO, tDV 11 ns CS to SCLK Setup and Hold, tS, tC 2 ns CS Minimum Pulse Width High, tPWH 3 ns |
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