MPC5633MMLL60 datasheet(22/106 Pages) FREESCALE

22 / 106 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

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Each interrupt source can be programmed to one of 16 priorities

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Preemptive prioritized interrupt requests to processor

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ISR at a higher priority preempts executing ISRs or tasks at lower priorities

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Automatic pushing or popping of preempted priority to or from a LIFO

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Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources

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Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor

This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.

2.3.5

FMPLL

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz crystal oscillator or external clock

generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication

factor, output clock divider ratio are all software configurable. The PLL has the following major features:

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Input clock frequency from 4 MHz to 20 MHz

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Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz, resulting in system clock frequencies from

16 MHz to 80 MHz with granularity of 4 MHz or better

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Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock

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3 modes of operation

— Bypass mode with PLL off

— Bypass mode with PLL running (default mode out of reset)

— PLL normal mode

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Each of the three modes may be run with a crystal oscillator or an external clock reference

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Programmable frequency modulation

— Modulation enabled/disabled through software

— Triangle wave modulation up to 100 kHz modulation frequency

— Programmable modulation depth (0% to 2% modulation depth)

— Programmable modulation frequency dependent on reference frequency

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Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to

report loss of lock conditions

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Clock Quality Module

— detects the quality of the crystal clock and cause interrupt request or system reset if error is detected

— detects the quality of the PLL output clock. If an error is detected, causes a system reset or switches the system

clock to the crystal clock and causes an interrupt request

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Programmable interrupt request or system reset on loss of lock

2.3.6

Calibration EBI

The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the VertiCal

connector in the calibration address space. The Calibration EBI is only available in the VertiCal Calibration System. The

Calibration EBI includes a memory controller that generates interface signals to support a variety of external memories. The

Calibration EBI memory controller supports legacy flash, SRAM, and asynchronous memories. In addition, the calibration EBI

supports up to three regions via chip selects (two chip selects are multiplexed with two address bits), along with programmed

region-specific attributes. The calibration EBI supports the following features:

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22-bit address bus (two most significant signals multiplexed with two chip selects)

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16-bit data bus

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Multiplexed mode with addresses and data signals present on the data lines

MPC5633MMLL60 数据表(PDF) 22 Page - Freescale Semiconductor, Inc

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