 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
MPC5633MMLL60 数据表(PDF) 99 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC5633MMLL60 数据表(HTML) 99 Page - Freescale Semiconductor, Inc |
|
|
99 / 106 page  MPC5634M Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 99 Figure 9. JTAG test clock input timing 12 tBSDVZ CC D TCK Falling Edge to Output Valid out of High Impedance —50 ns 13 tBSDHZ CC D TCK Falling Edge to Output High Impedance — 50 ns 14 tBSDST CC D Boundary Scan Input Valid to TCK Rising Edge 50 — ns 15 tBSDHT CC D TCK Rising Edge to Boundary Scan Input Invalid 50 — ns 1 JTAG timing specified at V DD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V with multi-voltage pads programmed to Low-Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 34 for functional specifications. Table 33. JTAG pin AC electrical characteristics1 (continued) # Symbol C Characteristic Min. Value Max. Value Unit TCK 1 2 2 3 3 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
