MPC5633MMLL60 datasheet(3/106 Pages) FREESCALE

3 / 106 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

– Operating on all 32 GPRs that are all extended to 64 bits wide

– Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including

integer vector MAC and MUL operations) (SIMD)

– Provides rich array of extended 64-bit loads and stores to/from extended GPRs

– Fully code compatible with e200z6 core

— Floating point

– IEEE 754 compatible with software wrapper

– Scalar single precision in hardware, double precision with software library

– Conversion instructions between single precision floating point and fixed point

– Fully code compatible with e200z6 core

— Long cycle time instructions, except for guarded loads, do not increase interrupt latency

— Extensive system development support through Nexus debug port

•

Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)

— Three master ports, four slave ports

– Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA

– Slave: Flash; SRAM; Peripheral Bridge; calibration EBI

— 32-bit internal address bus, 64-bit internal data bus

•

Enhanced direct memory access (eDMA) controller

— 32 channels support independent 8-bit, 16-bit, or 32-bit single value or block transfers

— Supports variable sized queues and circular queues

— Source and destination address registers are independently configured to post-increment or remain constant

— Each transfer is initiated by a peripheral, CPU, or eDMA channel request

— Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block

transfer

•

Interrupt controller (INTC)

— 191 peripheral interrupt request sources

— 8 software settable interrupt request sources

— 9-bit vector

– Unique vector for each interrupt request source

– Provided by hardware connection to processor or read from register

— Each interrupt source can be programmed to one of 16 priorities

— Preemption

– Preemptive prioritized interrupt requests to processor

– ISR at a higher priority preempts ISRs or tasks at lower priorities

– Automatic pushing or popping of preempted priority to or from a LIFO

– Ability to modify the ISR or task priority. Modifying the priority can be used to implement the Priority Ceiling

Protocol for accessing shared resources.

— Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor

•

Frequency Modulating Phase-locked loop (FMPLL)

— Reference clock pre-divider (PREDIV) for finer frequency synthesis resolution

— Reduced frequency divider (RFD) for reducing the FMPLL output clock frequency without forcing the FMPLL

to re-lock

— System clock divider (SYSDIV) for reducing the system clock frequency in normal or bypass mode

— Input clock frequency range from 4 MHz to 20 MHz before the pre-divider, and from 4 MHz to 16 MHz at the

FMPLL input

— Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz

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