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MPC5633MMLL60 数据表(PDF) 91 Page - Freescale Semiconductor, Inc |
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MPC5633MMLL60 数据表(HTML) 91 Page - Freescale Semiconductor, Inc |
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91 / 106 page  MPC5634M Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 91 GAINVGA1 CC – Variable gain amplifier accuracy (gain=1)9 CC C INL 8 MHz ADC –4 4 Counts10 CC C 16 MHz ADC –8 8 Counts CC C DNL 8 MHz ADC –311 311 Counts CC C 16 MHz ADC –311 311 Counts GAINVGA2 CC – Variable gain amplifier accuracy (gain=2)9 CC D INL 8 MHz ADC –5 5 Counts CC D 16 MHz ADC –8 8 Counts CC D DNL 8 MHz ADC –3 3 Counts CC D 16 MHz ADC –3 3 Counts GAINVGA4 CC – Variable gain amplifier accuracy (gain=4)9 CC D INL 8 MHz ADC –7 7 Counts CC D 16 MHz ADC –8 8 Counts CC D DNL 8 MHz ADC –4 4 Counts CC D 16 MHz ADC –4 4 Counts DIFFmax CC C Maximum differential voltage (DANx+ - DANx-) or (DANx- - DANx+) PREGAIN set to 1X setting –(VRH - VRL)/2 V DIFFmax2 CC C PREGAIN set to 2X setting –(VRH - VRL)/4 V DIFFmax4 CC C PREGAIN set to 4X setting –(VRH - VRL)/8 V DIFFcmv CC C Differential input Common mode voltage (DANx- + DANx+)/212 (VRH - VRL)/2 - 5% (VRH - VRL)/2 + 5% V 1 Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms. 2 At V RH – VRL = 5.12 V, one count = 1.25 mV. Without using pregain. 3 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater then VRH and 0x0 for values less then VRL. Other channels are not affected by non-disruptive conditions. 4 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 5 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values. 6 Condition applies to two adjacent pins at injection limits. 7 Performance expected with production silicon. 8 All channels have same 10 k <Rs<100k; Channel under test has Rs=10 k; I INJ=IINJMAX,IINJMIN 9 Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1, 2, or 4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated. Table 26. eQADC conversion specifications (operating) (continued) Symbol C Parameter Value Unit min max |
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