MPC5633MMLL60 datasheet(89/106 Pages) FREESCALE

89 / 106 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

VILEXT

T EXTAL input low voltage

Crystal Mode14,

0.65

Vxtal1.25V15

—Vxtal –

0.4

External Reference14,

0VRC33/2

– 0.4

—

T XTAL load capacitance12

4MHz

8MHz

12 MHz

16 MHz

20 MHz

tlpll

P PLL lock time 12, 17

—

200

s

tdc

T Duty cycle of reference

—40

fLCK

T Frequency LOCK range

—

–6

% fsys

fUL

T Frequency un-LOCK range

—

–18

% fsys

fCS

fDS

D Modulation Depth

Center spread

±0.25

±4.0

%fsys

Down Spread

–0.5

–8.0

fMOD

D Modulation frequency18

—

100

kHz

1 All values given are initial design targets and subject to change.

2 Considering operation with PLL not bypassed.

3 f

VCO is calculated as follows:

— In Legacy Mode fVCO =(fcrystal / (PREDIV + 1)) * (4 * (MFD + 4))

— In Enhanced Mode fvco = (fcrystal / (EPREDIV + 1)) * (EMFD + 4)

4 All internal registers retain data at 0 Hz.

5 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked

mode.

6 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the

fLOR window.

7 f

VCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in

enhanced mode.

8 This value is determined by the crystal manufacturer and board design.

9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

SYS.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.

Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the

CJITTER percentage for a given interval.

10 Proper PC board layout procedures must be followed to achieve specifications.

11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

JITTER and

either fCS or fDS (depending on whether center spread or down spread modulation is enabled).

12 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for

this PLL, load capacitors should not exceed these limits. For a 20 MHz crystal the maximum load should be 17 pF.

13 Proper PC board layout procedures must be followed to achieve specifications.

14 This parameter is guaranteed by design rather than 100% tested.

Table 24. PLLMRFM electrical specifications1

(VDDPLL =1.14 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued)

Symbol

Parameter

Conditions

Value

Unit

min

max

MPC5633MMLL60 数据表(PDF) 89 Page - Freescale Semiconductor, Inc

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