MPC5633MMLL60 datasheet(15/106 Pages) FREESCALE

15 / 106 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

— External interrupt inputs, filtering and control

— Critical Interrupt control

— Non-Maskable Interrupt control

— Internal multiplexer subblock (IMUX)

– Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external signals)

– Allows selection of interrupt requests between external pins and DSPI

•

Error correction status module (ECSM)

— Configurable error-correcting codes (ECC) reporting

— Single-bit error correction reporting

•

On-chip flash memory

— Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface

— 16 KB shadow block

— Fetch Accelerator

– Provide single cycle flash access at 80 MHz

– Quadruple 128-bit wide prefetch/burst buffers

– Prefetch buffers can be configured to prefetch code or data or both

— Censorship protection scheme to prevent flash content visibility

— Flash divided into two independent arrays, allowing reading from one array while erasing/programming the other

array (used for EEPROM emulation)

— Memory block:

– For MPC5634M: 18 blocks (4

16 KB, 2 32 KB, 2 64 KB, 10 128 KB)

– For MPC5633M: 14 blocks (4

16 KB, 2 32 KB, 2 64 KB, 6 128 KB)

– For MPC5632M: 12 blocks (4

16 KB, 2 32 KB, 2 64 KB, 4 128 KB)

— Hardware programming state machine

•

On-chip static RAM

— For MPC5634M: 94 KB general purpose RAM of which 32 KB are on standby power supply

— For MPC5633M: 64 KB general purpose RAM of which 24 KB are on standby power supply

— For MPC5632M: 48 KB general purpose RAM of which 24 KB are on standby power supply

•

Boot assist module (BAM)

— Enables and manages the transition of MCU from reset to user code execution in the following configurations:

– Execution from internal flash memory

– Execution from external memory on the calibration bus

– Download and execution of code via FlexCAN or eSCI

•

Periodic interrupt timer (PIT)

— 32-bit wide down counter with automatic reload

— Four channels clocked by system clock

— One channel clocked by crystal clock

— Each channel can produce periodic software interrupt

— Each channel can produce periodic triggers for eQADC queue triggering

— One channel out of the five can be used as wake-up timer to wake device from low power stop mode

•

System timer module (STM)

— 32-bit up counter with 8-bit prescaler

— Clocked from system clock

— Four-channel timer compare hardware

— Each channel can generate a unique interrupt request

MPC5633MMLL60 数据表(PDF) 15 Page - Freescale Semiconductor, Inc

MPC5633MMLL60 数据表(HTML) 15 Page - Freescale Semiconductor, Inc

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