MPC5633MMLL60 datasheet(27/106 Pages) FREESCALE

27 / 106 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

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32 channels, each channel is associated with one input and one output signal

— Enhanced input digital filters on the input pins for improved noise immunity.

— Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned

to more than one channel at a given time, so each signal can have any functionality.

— Each channel has an event mechanism which supports single and double action functionality in various

combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and

equal-only comparators

— Input and output signal states visible from the host

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2 independent 24-bit time bases for channel synchronization:

— First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by

output of second time base prescaler

— Second time base counter can work as a continuous angle counter, enabling angle based applications to match

angle instead of time

— Both time bases can be exported to the eMIOS timer module

— Both time bases visible from the host

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Event-triggered microengine:

— Fixed-length instruction execution in two-system-clock microcycle

— 14 KB of code memory (SCM)

— 3 KB of parameter (data) RAM (SPRAM)

— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected

combinations

— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value,

bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign

extension and conditional execution

— Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations,

and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands

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Resource sharing features support channel use of common channel registers, memory and microengine time:

— Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined,

host-configured priority

— Automatic channel context switch when a “task switch” occurs, i.e., one function thread ends and another begins

to service a request from other channel: channel-specific registers, flags and parameter base address are

automatically loaded for the next serviced channel

— SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or

inter-channel

— Dual-parameter coherency hardware support allows atomic access to two parameters by host

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Test and development support features:

— Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware

breakpoints and watchpoints on several conditions

— Software breakpoints

— SCM continuous signature-check built-in self test (MISC — multiple input signature calculator), runs

concurrently with eTPU2 normal operation

For MPC5634M, the eTPU2 has been further enhanced with these features:

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System enhancements

— Timebases and channels are run at full system clock speed

— Software watchdog with programmable timeout

— Real-time performance information

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Channel enhancements

MPC5633MMLL60 数据表(PDF) 27 Page - Freescale Semiconductor, Inc

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