MPC5633MMLL60 datasheet(28/106 Pages) FREESCALE

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MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

— Programmable channel mode allows customization of channel function

— Channels 1 and 2 can optionally drive angle clock hardware

•

Programming enhancements

— Engine relative addressing mode

— More flexibility in requesting DMA and interrupt service

— Channel flags can be tested

2.3.14

eQADC

The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of

applications. The eQADC provides a parallel interface to two on-chip analog to digital converters (ADC), and a single master

to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels.

The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the on-chip ADCs or to

the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six

result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having

the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort

a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a

deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger

occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands

from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result

queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system

memory, which is external to the eQADC.

The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used

in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for

increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics.

The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate,

passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate

results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band

noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully

process the digitized waveform.

The eQADC provides the following features:

•

Dual on-chip ADCs

—2

 12-bit ADC resolution

— Programmable resolution for increased conversion speed (12 bit, 10 bit, 8 bit)

– 12-bit conversion time – 1

s (1M sample/sec)

– 10-bit conversion time – 867 ns (1.2M sample/second)

– 8-bit conversion time – 733 ns (1.4M sample/second)

— Up to 10-bit accuracy at 500 KSample/s and 9-bit accuracy at 1 MSample/s

— Differential conversions

— Single-ended signal range from 0 to 5 V

— Variable gain amplifiers on differential inputs (

1, 2, 4)

— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

— Provides time stamp information when requested

— Parallel interface to eQADC CFIFOs and RFIFOs

— Supports both right-justified unsigned and signed formats for conversion results

•Up to 341 input channels (accessible by both ADCs)

1. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.

MPC5633MMLL60 数据表(PDF) 28 Page - Freescale Semiconductor, Inc

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