MPC8313VRGDDB datasheet(23/100 Pages) FREESCALE

23 / 100 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.2.1.1

MII Transmit AC Timing Specifications

Table 26 provides the MII transmit AC timing specifications.

Figure 8 shows the MII transmit AC timing diagram.

Figure 8. MII Transmit AC Timing Diagram

8.2.1.2

MII Receive AC Timing Specifications

Table 27 provides the MII receive AC timing specifications.

Table 26. MII Transmit AC Timing Specifications

At recommended operating conditions with LVDDA/LVDDB/NVDD of 3.3 V ± 0.3 V.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

TX_CLK clock period 10 Mbps

tMTX

—400

—

TX_CLK clock period 100 Mbps

tMTX

—40

—

TX_CLK duty cycle

tMTXH/tMTX

—

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

tMTKHDX

TX_CLK data clock rise VIL(min) to VIH(max)

tMTXR

1.0

—

4.0

TX_CLK data clock fall VIH(max) to VIL(min)

tMTXF

1.0

—

4.0

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit

timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

Table 27. MII Receive AC Timing Specifications

At recommended operating conditions with LVDDA/LVDDB/NVDD of 3.3 V ± 0.3 V.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

RX_CLK clock period 10 Mbps

tMRX

—400

—

RX_CLK clock period 100 Mbps

tMRX

—40

—

RX_CLK duty cycle

tMRXH/tMRX

—

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

tMRDVKH

10.0

—

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

MPC8313VRGDDB 数据表(PDF) 23 Page - Freescale Semiconductor, Inc

MPC8313VRGDDB 数据表(HTML) 23 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表下载

链接网址

MPC8313VRGDDB 数据表(PDF) 23 Page - Freescale Semiconductor, Inc

MPC8313VRGDDB 数据表(HTML) 23 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表 下载

链接网址

数据表下载