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MPC8313VRGDDB 数据表(PDF) 18 Page - Freescale Semiconductor, Inc |
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MPC8313VRGDDB 数据表(HTML) 18 Page - Freescale Semiconductor, Inc |
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18 / 100 page  MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1 18 Freescale Semiconductor DDR and DDR2 SDRAM MDQS epilogue end tDDKHME –0.6 0.6 ns 6 Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, for a description and understanding of the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1. Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Silicon Rev 2.x or Later Parameter Symbol1 Min Max Unit Notes MCK[ n] cycle time, MCK[n]/MCK[n] crossing tMCK 610 ns 2 ADDR/CMD output setup with respect to MCK tDDKHAS ns 3 333 MHz 2.1 — 266 MHz 2.5 — ADDR/CMD output hold with respect to MCK tDDKHAX ns 3 333 MHz 2.0 — 266 MHz 2.7 — MCS[ n] output setup with respect to MCK tDDKHCS ns 3 333 MHz 2.1 — 266 MHz 3.15 — MCS[ n] output hold with respect to MCK tDDKHCX ns 3 333 MHz 2.0 — 266 MHz 2.7 — MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4 MDQ//MDM output setup with respect to MDQS tDDKHDS, tDDKLDS ps 5 333 MHz 800 — 266 MHz 900 — MDQ//MDM output hold with respect to MDQS tDDKHDX, tDDKLDX ps 5 333 MHz 750 — 266 MHz 1000 — Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Rev. 1.0 Silicon (continued) Parameter Symbol 1 Min Max Unit Notes |
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