MPC8313VRGDDB datasheet(26/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

Figure 12 provides the AC test load.

Figure 12. AC Test Load

Figure 13 shows the RMII receive AC timing diagram.

Figure 13. RMII Receive AC Timing Diagram

8.2.2

RGMII and RTBI AC Timing Specifications

Table 30 presents the RGMII and RTBI AC timing specifications.

REF_CLK clock fall time VIH(max) to VIL(min)

tRMXF

1.0

—

4.0

Note:

1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII

receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock

reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect to

the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold time.

Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

Table 30. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LVDDA/LVDDB of 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)

tSKRGT

–0.5

—

0.5

Data to clock input skew (at receiver) 2

tSKRGT

1.0

—

2.8

Clock cycle duration 3

tRGT

7.2

8.0

8.8

Duty cycle for 1000Base-T 4, 5

tRGTH/tRGT

Table 29. RMII Receive AC Timing Specifications (continued)

At recommended operating conditions with NVDD of 3.3 V ± 0.3 V.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Output

Z0 = 50 Ω

NVDD/2

RL = 50 Ω

REF_CLK

RXD[1:0]

tRMRDXKH

tRMX

tRMXH

tRMXR

tRMXF

CRS_DV

RX_ER

tRMRDVKH

Valid Data

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