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MPC8313VRGDDB 数据表(PDF) 41 Page - Freescale Semiconductor, Inc

部件名 MPC8313VRGDDB
功能描述  PowerQUICC??II Pro Processor Hardware Specifications
PDF  100 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8313VRGDDB 数据表(HTML) 41 Page - Freescale Semiconductor, Inc

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MPC8313E PowerQUICCII Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
41
High-Speed Serial Interfaces (HSSI)
NOTE
Figure 27 to Figure 30 are for conceptual reference only. Due to the fact that
the clock driver chip's internal structure, output impedance, and termination
requirements are different between various clock driver chip manufacturers,
it is possible that the clock circuit reference designs provided by clock
driver chip vendors are different from what is shown in the figures. They
might also vary from one vendor to the other. Therefore, Freescale can
neither provide the optimal clock driver reference circuits, nor guarantee the
correctness of the following clock driver connection reference circuits. It is
recommended that the system designer contact the selected clock driver
chip vendor for the optimal reference circuits for the MPC8313E SerDes
reference clock receiver requirement provided in this document.
Figure 27 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with MPC8313E SerDes reference clock
input’s DC requirement.
Figure 27. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 28 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common mode voltage is higher than the MPC8313E SerDes reference clock
input’s allowed range (100 to 400 mV), the AC-coupled connection scheme must be used. It assumes the
LVDS output driver features a 50-
Ω termination resistor. It also assumes that the LVDS transmitter
establishes its own common mode level without relying on the receiver or other external component.
50
Ω
50
Ω
SD
n_REF_CLK
SDn_REF_CLK
Clock Driver
100
Ω Differential PWB Trace
Clock driver vendor dependent
source termination resistor
CLK_Out
CLK_Out
HCSL CLK Driver Chip
33
Ω
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
MPC8313E
SerDes Refer.
CLK Receiver
Clock Driver
SD
n_REF_CLK



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