MPC8313VRGDDB datasheet(35/100 Pages) FREESCALE

35 / 100 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.5.2

MII Management AC Electrical Specifications

Table 39 provides the MII management AC timing specifications.

Table 38. MII Management DC Electrical Characteristics When Powered at 3.3 V

Parameter

Symbol

Conditions

Min

Max

Unit

Supply voltage (3.3 V) NVDDA/NVDDB

—

2.97

3.63

Output high voltage

VOH

IOH = –1.0 mA

NVDDA or NVDDB = Min

2.10

NVDDA +0.3

NVDDB +0.3

Output low voltage

VOL

IOL = 1.0 mA

LVDDA or LVDDB = Min

VSS

0.50

Input high voltage

VIH

—2.0

—

Input low voltage

VIL

——

0.80

Input high current

IIH

NVDDA or NVDDB = Max

VIN

1 = 2.1 V

—

μA

Input low current

IIL

NVDDA or NVDDB = Max

VIN = 0.5 V

–600

—

μA

Note:

1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.

Table 39. MII Management AC Timing Specifications

At recommended operating conditions with LVDDA/LVDDB is 3.3 V ± 0.3V or 2.5 V ± 5%

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Notes

MDC frequency

fMDC

—2.5

—

MHz

MDC period

tMDC

—

400

—

MDC clock pulse width high

tMDCH

—

MDC to MDIO delay

tMDKHDX

—

170

MDIO to MDC setup time

tMDDVKH

5—

—

MDIO to MDC hold time

tMDDXKH

0—

—

MDC rise time

tMDCR

—

MDC fall time

tMDHF

—

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management

data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state

(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt Clock Select] field determines the clock frequency

of the Mgmt Clock EC_MDC.)

MPC8313VRGDDB 数据表(PDF) 35 Page - Freescale Semiconductor, Inc

MPC8313VRGDDB 数据表(HTML) 35 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表下载