MPC8313VRGDDB datasheet(31/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.3.4.1

SGMII Transmit AC Timing Specifications

Table 34 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.

8.3.4.2

SGMII Receive AC Timing Specifications

Table 35 provides the SGMII receive AC timing specifications. Source synchronous clocking is not

supported. Clock is recovered from the data. Figure 17 shows the SGMII receiver input compliance mask

eye diagram.

Table 34. SGMII Transmit AC Timing Specifications

At recommended operating conditions with XCOREVDD = 1.0 V ± 5%.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Deterministic jitter

—

0.17

UI p-p

Total jitter

—

0.35

UI p-p

Unit interval

799.92

800

800.08

VOD fall time (80%–20%)

tfall

—

120

VOD rise time (20%–80%)

trise

—

120

Note:

1. Each UI is 800 ps ± 100 ppm.

Table 35. SGMII Receive AC Timing Specifications

At recommended operating conditions with XCOREVDD = 1.0 V ± 5%.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Deterministic jitter tolerance

0.37

—

UI p-p

Combined deterministic and random jitter tolerance

JDR

0.55

—

UI p-p

Sinusoidal jitter tolerance

JSIN

0.1

—

UI p-p

Total jitter tolerance

0.65

—

UI p-p

Bit error ratio

BER

—

10–12

Unit interval

799.92

800

800.08

AC coupling capacitor

CTX

5—

200

Notes:

1. Measured at receiver.

2. Each UI is 800 ps ± 100 ppm.

3. The external AC coupling capacitor is required. It is recommended to be placed near the device transmitter outputs.

4. Refer to the

RapidIO™ 1x/4x LP Serial Physical Layer Specification, for interpretation of jitter specifications.

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