MPC8313VRGDDB datasheet(89/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

System Design Information

The SDAVDD signal provides power for the analog portions of the SerDes PLL. To ensure stability of the

internal clock, the power supplied to the PLL is filtered using a circuit like the one shown in Figure 59.

For maximum effectiveness, the filter circuit should be placed as closely as possible to the SDAVDD ball

to ensure it filters out as much noise as possible. The ground connection should be near the SDAVDD ball.

The 0.003-µF capacitor is closest to the ball, followed by the two 2.2-µF capacitors, and finally the 1-

resistor to the board supply plane. The capacitors are connected from traces from SDAVDD to the ground

plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be

kept short, wide, and direct.

Figure 59. SerDes PLL Power Supply Filter Circuit

Note the following:

•SDAVDD should be a filtered version of XCOREVDD.

•

Output signals on the SerDes interface are fed from the XPADVDD power plane. Input signals and

sensitive transceiver analog circuits are on the XCOREVDD supply.

•

Power: XPADVDD consumes less than 300 mW; XCOREVDD +SDAVDD consumes less than

750 mW.

22.3

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8313E system, and the

MPC8313E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that

the system designer place at least one decoupling capacitor at each VDD, NVDD, GVDD, LVDD, LVDDA,

and LVDDB pin of the device. These decoupling capacitors should receive their power from separate VDD,

NVDD, GVDD, LVDD, LVDDA, LVDDB, and VSS power planes in the PCB, utilizing short traces to

minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern.

Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the VDD, NVDD, GVDD, LVDD, LVDDA, and LVDDB planes, to enable quick recharging of the

smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating

to ensure the quick response time necessary. They should also be connected to the power and ground

planes through two vias to minimize inductance. Suggested bulk capacitors—100 to 330 µF (AVX TPS

tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor

for best values and types of bulk capacitors.

Note:

1. An 0805 sized capacitor is recommended for system initial bring-up.

XCOREVDD

SDAVDD

SDAVSS

2.2 µF1

0.003 µF

1.0

2.2 µF1

MPC8313VRGDDB 数据表(PDF) 89 Page - Freescale Semiconductor, Inc

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