 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
MPC8313VRGDDB 数据表(PDF) 77 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8313VRGDDB 数据表(HTML) 77 Page - Freescale Semiconductor, Inc |
|
|
77 / 100 page  MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1 Freescale Semiconductor 77 Clocking 20 Clocking Figure 57 shows the internal distribution of clocks within the MPC8313E. 1 Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL]. 2 Multiplication factor L = 2, 3, 4, 5, and 6. Value is decided by RCWLR[SPMF]. Figure 57. MPC8313E Clock Subsystem System LBC LCLK[0:1] e300c3 Core csb_clk to Rest csb_clk MPC8313E Local Bus PCI_CLK_OUT[0:2] PCI_SYNC_OUT PCI_CLK/ Clock Unit of the Device lbc_clk PCI Clock PCI_SYNC_IN Memory Device /n To Local Bus Clock Divider ( ÷2) 3 MEMC_MCK MEMC_MCK DDR ddr_clk DDR Memory Device PLL To DDR Memory Controller Clock CFG_CLKIN_DIV /2 Divider Divider 1 0 USB Mac USB PHY PLL eTSEC Protocol Converter GTX_CLK125 125-MHz Source SYS_CR_CLK_IN SYS_CR_CLK_OUT mux Crystal SYS_CLK_IN USB_CR_CLK_IN USB_CR_CLK_OUT Crystal USB_CLK_IN /1,/2 RTC_CLK (32 kHz) RTC Sys Ref Core PLL core_clk x L2 x M1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
