ATtiny13A datasheet(65/174 Pages) ATMEL

65 / 174 page

8126D–AVR–11/09

ATtiny13A

The timing diagram for the CTC mode is shown in Figure 11-5 on page 65. The counter value

(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then coun-

ter (TCNT0) is cleared.

Figure 11-5. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0A is lower than the current

value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can

occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical

level on each Compare Match by setting the Compare Output mode bits to toggle mode

(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of fOC0 =

fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

11.7.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by

its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match

between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the out-

put is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the

operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

TCNTn

OCn

(Toggle)

OCnx Interrupt Flag Set

Period

(COMnx1:0 = 1)

fOCnx

fclk_I/O

2 N

1 OCRnx

()

⋅⋅

--------------------------------------------------

ATtiny13A 数据表(PDF) 65 Page - ATMEL Corporation

ATtiny13A 数据表(HTML) 65 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载