ATtiny13A datasheet(86/174 Pages) ATMEL

86 / 174 page

8126D–AVR–11/09

ATtiny13A

When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in

Figure 14-6 below. This assures a fixed delay from the trigger event to the start of conversion. In

this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the

trigger source signal. Three additional CPU clock cycles are used for synchronization logic.

Figure 14-6. ADC Timing Diagram, Auto Triggered Conversion

In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high.

Figure 14-7. ADC Timing Diagram, Free Running Conversion

Sign and MSB of Result

LSB of Result

ADC Clock

Trigger

Source

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Prescaler

Reset

ADATE

Prescaler

Reset

Sample &

Hold

MUX and REFS

Update

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Sample & Hold

MUX and REFS

Update

ATtiny13A 数据表(PDF) 86 Page - ATMEL Corporation

ATtiny13A 数据表(HTML) 86 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载