ATtiny13A datasheet(47/174 Pages) ATMEL

47 / 174 page

8126D–AVR–11/09

ATtiny13A

9.3

9.3.1

MCUCR – MCU Control Register

The External Interrupt Control Register A contains control bits for interrupt sense control.

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 9-2 on page 47. The value on the INT0 pin is sampled before

detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock

period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If

low level interrupt is selected, the low level must be held until the completion of the currently

executing instruction to generate an interrupt.

9.3.2

GIMSK – General Interrupt Mask Register

• Bits 7, 4:0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU

Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-

ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even

if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is

executed from the INT0 Interrupt Vector.

• Bit 5 – PCIE: Pin Change Interrupt Enable

When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt is enabled. Any change on any enabled PCINT5..0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt

Vector. PCINT5..0 pins are enabled individually by the PCMSK Register.

Bit

65432

0x35

–

PUD

SM1

SM0

–

ISC01

ISC00

MCUCR

Read/Write

R/W

Initial Value

00000

Table 9-2.

Interrupt 0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

Bit

76543210

0x3B

–

INT0

PCIE

–––––

GIMSK

Read/Write

R/W

RRRRR

Initial Value

00000000

ATtiny13A 数据表(PDF) 47 Page - ATMEL Corporation

ATtiny13A 数据表(HTML) 47 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载