ATtiny13A datasheet(34/174 Pages) ATMEL

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8126D–AVR–11/09

ATtiny13A

• Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1:0

These bits select between the three available sleep modes as shown in Table 7-2 on page 34.

7.5.3

PRR – Power Reduction Register

The Power Reduction Register provides a method to reduce power consumption by allowing

peripheral clock signals to be disabled.

• Bits 7:2 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bit 1 – PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

• Bit 0 – PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.

The analog comparator cannot be used when the ADC is shut down.

Table 7-2.

Sleep Mode Select

SM1

SM0

Sleep Mode

Idle

ADC Noise Reduction

Power-down

Reserved

Bit

654

0x25

–

PRTIM0

PRADC

PRR

Read/Write

R/W

Initial Value

ATtiny13A 数据表(PDF) 34 Page - ATMEL Corporation

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