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ATtiny13A 数据表(PDF) 3 Page - ATMEL Corporation |
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ATtiny13A 数据表(HTML) 3 Page - ATMEL Corporation |
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3 / 174 page ![]() 3 8126D–AVR–11/09 ATtiny13A 1.1 Pin Description 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB5:PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13A as listed on page 55. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The min- imum pulse length is given in Table 18-4 on page 120. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. |
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