ATtiny13A datasheet(33/174 Pages) ATMEL

33 / 174 page

8126D–AVR–11/09

ATtiny13A

7.4.6

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important thing is then to ensure that no pins drive resistive loads. In sleep modes where

both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device

will be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 53 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an

analog signal level close to VCC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to VCC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to

“DIDR0 – Digital Input Disable Register 0” on page 81 for details.

7.5

7.5.1

BODCR – Brown-Out Detector Control Register

The BOD Control Register contains control bits for disabling the BOD by software.

• Bit 1 – BODS: BOD Sleep

In order to disable BOD during sleep the BODS bit must be written to logic one. This is controlled

by a timed sequence and the enable bit, BODSE. First, both BODS and BODSE must be set to

one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to

zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be exe-

cuted while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit

is automatically cleared after three clock cycles.

• Bit 0 – BODSE: BOD Sleep Enable

The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD

disable is controlled by a timed sequence.

7.5.2

MCUCR – MCU Control Register

The MCU Control Register contains control bits for power management.

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

Bit

654

0x30

–

BODS

BODSE

BODCR

Read/Write

R/W

Initial Value

Bit

654

0x35

–

PUD

SM1

SM0

–

ISC01

ISC00

MCUCR

Read/Write

R/W

Initial Value

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