ATtiny13A datasheet(72/174 Pages) ATMEL

72 / 174 page

8126D–AVR–11/09

ATtiny13A

Table 11-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM

mode.

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 65

for more details.

Table 11-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 67 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

Table 11-5.

Compare Output Mode, non-PWM Mode

COM0B1

COM0B0

Description

Normal port operation, OC0B disconnected.

Toggle OC0B on Compare Match

Clear OC0B on Compare Match

Set OC0B on Compare Match

Table 11-6.

Compare Output Mode, Fast PWM Mode(1)

COM0B1

COM0B0

Description

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match, set OC0B at TOP

Set OC0B on Compare Match, clear OC0B at TOP

Table 11-7.

Compare Output Mode, Phase Correct PWM Mode(1)

COM0B1

COM0B0

Description

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match when up-counting. Set OC0B on

Compare Match when down-counting.

Set OC0B on Compare Match when up-counting. Clear OC0B on

Compare Match when down-counting.

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