ATtiny13A datasheet(38/174 Pages) ATMEL

38 / 174 page

8126D–AVR–11/09

ATtiny13A

8.2.4

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to

“Interrupts” on page 45 for details on operation of the Watchdog Timer.

Figure 8-6.

Watchdog Reset During Operation

8.3

Internal Voltage Reference

ATtiny13A features an internal bandgap reference. This reference is used for Brown-out Detec-

tion, and it can be used as an input to the Analog Comparator or the ADC.

8.3.1

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in “System and Reset Characteristics” on page 120. To save power, the

reference is not always turned on. The reference is on during the following situations:

• When the BOD is enabled (by programming the BODLEVEL [1..0] fuse).

• When the bandgap reference is connected to the Analog Comparator (by setting the ACBG

bit in ACSR).

• When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

8.4

Watchdog Timer

ATtiny13A has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a

separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the

counter reaches a given time-out value. In normal operation mode, it is required that the system

uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out

ATtiny13A 数据表(PDF) 38 Page - ATMEL Corporation