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ATtiny13A 数据表(PDF) 73 Page - ATMEL Corporation |
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ATtiny13A 数据表(HTML) 73 Page - ATMEL Corporation |
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73 / 174 page  73 8126D–AVR–11/09 ATtiny13A • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form generation to be used, see Table 11-8 on page 73. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 64). Notes: 1. MAX = 0xFF 2. BOTTOM = 0x00 11.9.2 TCCR0B – Timer/Counter Control Register B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare. A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. Table 11-8. Waveform Generation Mode Bit Description Mode WGM2 WGM1 WGM0 Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on(1)(2) 0 0 0 0 Normal 0xFF Immediate MAX 1 001 PWM (Phase Correct) 0xFF TOP BOTTOM 2 010 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF TOP MAX 4 100 Reserved – – – 5 101 PWM (Phase Correct) OCRA TOP BOTTOM 6 110 Reserved – – – 7 111 Fast PWM OCRA TOP TOP Bit 7 6 5 4 3 210 0x33 FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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