ATtiny13A datasheet(20/174 Pages) ATMEL

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8126D–AVR–11/09

ATtiny13A

5.4

I/O Memory

The I/O space definition of the ATtiny13A is shown in “Register Summary” on page 155.

All ATtiny13A I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O Registers within the address range

0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

instruction set section for more details. When using the I/O specific commands IN and OUT, the

I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using

LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

5.5

5.5.1

EEARL – EEPROM Address Register

• Bits 7:6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bits 5:0 – EEAR[5:0]: EEPROM Address

The EEPROM Address Register – EEARL – specifies the EEPROM address in the 64 bytes

EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63. The initial

value of EEARL is undefined. A proper value must be written before the EEPROM may be

accessed.

5.5.2

EEDR – EEPROM Data Register

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEARL Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEARL.

Bit

543

0x1E

–

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

EEARL

Read/Write

R/W

Initial Value

Bit

654

0x1D

EEDR7

EEDR6

EEDR5

EEDR4

EEDR3

EEDR2

EEDR1

EEDR0

EEDR

Read/Write

R/W

Initial Value

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