 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
KM416RD8ACD-RK80 数据表(PDF) 48 Page - Samsung semiconductor |
|
|
|||||||||||||||||||||||||||||
KM416RD8ACD-RK80 数据表(HTML) 48 Page - Samsung semiconductor |
|
|
48 / 64 page  Page 45 KM416RD8AC(D)/KM418RD8AC(D) Direct RDRAM™ Rev. 1.01 Oct. 1999 tDR1, tDF1 SIO0, SIO1 input rise and fall times - 5.0 ns Figure 56 tDR2, tDF2 CMD, SCK input rise and fall times - 2.0 ns Figure 56 tCYCLE1 SCK cycle time - Serial control register transactions 1000 - ns Figure 56 SCK cycle time - Power transitions 10 - ns Figure 56 tCH1, tCL1 SCK high and low times 4.25 - ns Figure 56 tS1 CMD setup time to SCK rising or falling edgee 1 - ns Figure 56 tH1 CMD hold time to SCK rising or falling edgee 1 - ns Figure 56 tS2 SIO0 setup time to SCK falling edge 40 - ns Figure 56 tH2 SIO0 hold time to SCK falling edge 40 - ns Figure 56 tS3 PDEV setup time on DQA5..0 to SCK rising edge. 0 - ns Figure 48, Figure 57 tH3 PDEV hold time on DQA5..0 to SCK rising edge. 5.5 - ns tS4 ROW2..0, COL4..0 setup time for quiet window -1 - tCYCLE Figure 48 tH4 ROW2..0, COL4..0 hold time for quiet windowf 5 - tCYCLE Figure 48 vIL,CMOS CMOS input low voltage - over/undershoot voltage duration is less than or equal to 5ns - 0.7 VCMOS/2 - 0.6 V vIH,CMOS CMOS input high voltage - over/undershoot voltage duration is less than or equal to 5ns VCMOS/2 + 0.6 VCMOS + 0.7 V tNPQ Quiet on ROW/COL bits during NAP/PDN entry 4 - tCYCLE Figure 47 tREADTOCC Offset between read data and CC packets (same device) 12 - tCYCLE Figure 51 tCCSAMTOREAD Offset between CC packet and read data (same device) 8 - tCYCLE Figure 51 tCE CTM/CFM stable before NAP/PDN exit 2 - tCYCLE Figure 48 tCD CTM/CFM stable after NAP/PDN entry 100 - tCYCLE Figure 47 tFRM ROW packet to COL packet ATTN framing delay 7 - tCYCLE Figure 46 tNLIMIT Maximum time in NAP mode 10.0 µs Figure 45 tREF Refresh interval 32 ms Figure 50 tCCTRL Current control interval 34 tCYCLE 100ms ms/tCYCLE Figure 51 tTEMP Temperature control interval 100 ms Figure 52 tTCEN TCE command to TCAL command 150 - tCYCLE Figure 52 tTCAL TCAL command to quiet window 2 2 tCYCLE Figure 52 tTCQUIET Quiet window (no read data) 140 - tCYCLE Figure 52 tPAUSE RDRAM delay (no RSL operations allowed) 200.0 µs page 28 a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0. b. This parameter also applies to a -800 or -711 part when operated with tCYCLE=3.33ns. c. This parameter also applies to a -800 part when operated with tCYCLE=2.81ns. d. tS,MIN and tH,MIN for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values. e. With VIL,CMOS=0.5VCMOS-0.6V and VIH,CMOS=0.5VCMOS+0.6V f. Effective hold becomes tH4’= tH4+[PDNXA•64•tSCYCLE+tPDNXB,MAX]-[PDNX•256•tSCYCLE] if [PDNX•256•tSCYCLE] < [PDNXA•64•tSCYCLE+tPDNXB,MAX]. See Figure 48. Table 19: Timing Conditions Symbol Parameter Min Max Unit Figure(s) |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
