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KM416RD8ACD-RK80 数据表(PDF) 14 Page - Samsung semiconductor |
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KM416RD8ACD-RK80 数据表(HTML) 14 Page - Samsung semiconductor |
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14 / 64 page  Page 11 KM416RD8AC(D)/KM418RD8AC(D) Direct RDRAM™ Rev. 1.01 Oct. 1999 Figure 5: Mapping Between COLM Packet and D Packet for WR Command CTM/CFM COL4 COL3 COL2 COL1 COL0 T17 T18 T19 T20 MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2 CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T0 T4 T8 T12 T1 T5 T9 T13 T2 T6 T10 T14 T3 T7 T11 T15 T16 T20 T24 T28 T17 T21 T25 T29 T18 T22 T26 T30 T19 T23 T27 T31 T32 T36 T40 T44 T33 T37 T41 T45 T34 T38 T42 T46 T35 T39 T43 T47 MSK (a1) retire (a1) WR a1 D (a1) ACT b0 ACT a0 Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a3 = {Da,Ba} tRTR T19 T20 T21 T22 CTM/CFM DQB8 DQB7 DQB1 DQB0 DB71 DB8 DB17 DB26 DB35 DB45 DB53 DB62 DB7 DB16 DB25 DB34 DB44 DB52 DB61 DB70 DB1 DB10 DB19 DB28 DB37 DB46 DB55 DB64 DB0 DB9 DB18 DB27 DB36 DB45 DB54 DB63 COLM Packet PRER a2 DQA8 DQA7 DQA1 DQA0 D Packet MB0 DA71 DA8 DA17 DA26 DA35 DA45 DA53 DA62 DA7 DA16 DA25 DA34 DA44 DA52 DA61 DA70 DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64 DA0 DA9 DA18 DA27 DA36 DA45 DA54 DA63 MA0 MB1 MA1 MB2 MA2 MB3 MA3 MB4 MA4 MB5 MA5 MB6 MA6 MB7 MA7 tCWD Each bit of the MB7..MB0 field controls writing (=1) or no writing (=0) of the indicated DB bits when the M bit of the COLM packet is one. Each bit of the MA7..MA0 field controls writing (=1) or no writing (=0) of the indicated DA bits when the M bit of the COLM packet is one. When M=1, the MA and MB fields control writing of individual data bytes. When M=0, all data bytes are written unconditionally. |
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