KM416RD8ACD-RK80 datasheet(32/64 Pages) SAMSUNG

32 / 64 page

Page 29

KM416RD8AC(D)/KM418RD8AC(D)

Direct RDRAM™

Rev. 1.01 Oct. 1999

ο 3.13 Write CCA and CCB Register - These registers

are written with a value halfway between their minimum

and maximum values. This shortens the time needed for

the RDRAMs to reach their steady-state current control

values in stage 5.0.

ο 3.14 Powerdown Exit - The RDRAMs are in the PDN

power state at this point. A broadcast PDNExit command

is performed by the SIO block to place the RDRAMs in

the RLX (relax) power state in which they are ready to

receive ROW packets.

ο 3.15 SETF - Each RDRAM is given a SETF command

through the SIO block. One of the operations performed

by this step is to generate a value for the AS (autoskip) bit

in the SKIP register and fix the RDRAM to a particular

read domain.

4.0 Controller Configuration - This stage initializes the

controller block. Each step of this stage will set a field of the

ConfigRMC[63:0] bus to the appropriate value. Other

controller implementations will have similar initialization

requirements, and this stage may be used as a guide.

ο 4.1 Initial Read Data Offsets - The configRMC bus is

written with a value which determines the time interval

between a COL packet with a memory read command and

the Q packet with the read data on the Channel. The value

written sets RMC.d1 to the minimum value permitted for

the system. This will be adjusted later in stage 6.0.

ο 4.2 Configure Row/Column Timing - This step deter-

mines the values of the tRAS,MIN, tRP,MIN, tRC,MIN,

tRCD,MIN, tRR,MIN, and tPP,MIN RDRAM timing parame-

ters that are present in the system. The ConfigRMC bus is

written with values that will be compatible with all

RDRAM devices that are present.

ο 4.3 Set Refresh Interval - This step determines the

values of the tREF,MAX RDRAM timing parameter that are

present in the system. The ConfigRMC bus is written with

a value that will be compatible with all RDRAM devices

that are present.

ο 4.4 Set Current Control Interval - This step deter-

mines the values of the tCCTRL,MAX RDRAM timing

parameter that are present in the system. The ConfigRMC

bus is written with value that will be compatible with all

RDRAM devices that are present.

ο 4.5 Set Slew Rate Control Interval - This step deter-

mines the values of the tTEMP,MAX RDRAM timing

parameter that are present in the system. The ConfigRMC

bus is written with a value that will be compatible with all

RDRAM devices that are present.

ο 4.6 Set Bank/Row/Col Address Bits - This step deter-

mines the number of RDRAM bank, row, and column

address bits that are present in the system. It also deter-

mines the RDRAM core types (independent, doubled, or

split) that are present. The ConfigRMC bus is written with

a value that will be compatible with all RDRAM devices

that are present.

5.0 RDRAM Current Control - This step causes the INIT

block to generate a sequence of pulses which performs

RDRAM maintenance operations.

6.0 RDRAM Core, Read Domain Initialization - This

stage completes the RDRAM initialization

ο 6.1 RDRAM Core Initialization - A sequence of 192

memory refresh transactions is performed in order to place

the cores of all RDRAMs into the proper operating state.

ο 6.2 RDRAM Read Domain Initialization - A memory

write and memory read transaction is performed to each

RDRAM to determine which read domain each RDRAM

occupies. The programmed delay of each RDRAM is then

adjusted so the total RDRAM read delay (propagation

delay plus programmed delay) is constant. The TPARM

and TCDLYI registers of each RDRAM are rewritten with

the appropriate read delay values. The ConfigRMC bus is

also rewritten with an updated value.

7.0 Other RDRAM Register Fields - This stage rewrites

the INIT register with the final values of the LSR,NSR, and

PSR fields.

In essence, the controller must read all the read-only config-

uration registers of all RDRAMs (or it must read the SPD

device present on each RIMM), it must process this informa-

tion, and then it must write all the read-write registers to

place the RDRAMs into the proper operating mode.

Initialization Note [1]: During the initialization process, it is

necessary for the controller to perform 128 current control

operations (3xCAL, 1xCAL/SAM) and one temperature

calibrate operation (TCEN/TCAL) after reset or after power-

down (PDN)exit.

Initialization Note [2]: There are two classes of 64/72Mbit

RDRAM . They are distinguished by the “S28IECO” bit in

the SPD. The behavior of the RDRAM at initialization is

slightly different for the two types:

S28IECO=0: Upon powerup the device enters ATTN state.

The serial operations SETR, CLRR and SETF are performed

without requiring a SDEVID match of the SBC bit (broad-

cast) to be set.

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