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KM416RD8ACD-RK80 数据表(PDF) 33 Page - Samsung semiconductor |
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KM416RD8ACD-RK80 数据表(HTML) 33 Page - Samsung semiconductor |
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33 / 64 page  Page 30 KM416RD8AC(D)/KM418RD8AC(D) Direct RDRAM™ Rev. 1.01 Oct. 1999 S28IECO=1: Upon powerup the device enters PDN state. The serial operations SETR, CLRR, and SETF require a SDEVID match. See the document detailing the reference initialization proce- dure for more information on how to handle this in a system. Initialization Note [3]: After the step of equalizing the total read delay of each RDRAM has been completed (i.e.after the TCDLY0 and TCDLY1 fields have been written for the final time), a single final memory read transaction should be made to each RDRAM in order to ensure that the output pipeline stages have been cleared. Initialization Note [4]: The SETF command (in the serial SRQ packet) should only be issued once during the Initial- ization process, as should the SETR and CLRR commands. Initialization Note [5]: The CLRR command (in the serial SRQ packet) leaves some of the contents of the memory core in an indeterminate state. Control Register Summary Table 16 summarizes the RDRAM control registers. Detail is provided for each control register in Figure 27 through Figure 43. Read-only bits which are shaded gray are unused and return zero. Read-write bits which are shaded gray are reserved and should always be written with zero. The RIMM SPD Application Note describes additional read-only configuration registers which are present on Direct RIMMs. The state of the register fields are potentially affected by the IO Reset operation or the SETR/CLRR operation. This is indicated in the text accompanying each register diagram. Table 16: Control Register Summary SA11..SA0 Register Field read-write/ read-only Description 02116 INIT SDEVID read-write, 6 bits Serial device ID. Device address for control register read/write. PSX read-write, 1 bit Power select exit. PDN/NAP exit with device addr on DQA5..0. SRP read-write, 1 bit SIO repeater. Used to initialize RDRAM. NSR read-write, 1 bit NAP self-refresh. Enables self-refresh in NAP mode. PSR read-write, 1 bit PDN self-refresh. Enables self-refresh in PDN mode. LSR read-write, 1 bit Low power self-refresh. Enables low power self-refresh. TEN read-write, 1 bit Temperature sensing enable. TSQ read-write, 1 bit Temperature sensing output. DIS read-write, 1 bit RDRAM disable. 02216 TEST34 TEST34 read-write, 16 bits Test register. Do not read or write after SIO reset. 02316 CNFGA REFBIT read-only, 3 bit Refresh bank bits. Used for multi-bank refresh. DBL read-only, 1 bit Double. Specifies doubled-bank architecture MVER read-only, 6 bit Manufacturer version. Manufacturer identification number. PVER read-only, 6 bit Protocol version. Specifies version of Direct protocol supported. 02416 CNFGB BYT read-only, 1 bit Byte. Specifies an 8-bit or 9-bit byte size. DEVTYP read-only, 3 bit Device type. Device can be RDRAM or some other device category. SPT read-only, 1 bit Split-core. Each core half is an individual dependent core. CORG read-only, 6 bit Core organization. Bank, row, column address field sizes. SVER read-only, 6 bit Stepping version. Mask version number. 04016 DEVID DEVID read-write, 5 bits Device ID. Device address for memory read/write. 04116 REFB REFB read-write, 4 bits Refresh bank. Next bank to be refreshed by self-refresh. 04216 REFR REFR read-write, 9 bits Refresh row. Next row to be refreshed by REFA, self-refresh. 04316 CCA CCA read-write, 7 bits Current control A. Controls IOL output current for DQA. ASYMA read-write, 2 bits Asymmetry control. Controls asymmetry of VOL/VOH swing for DQA. 04416 CCB CCB read-write, 7 bits Current control B. Controls IOL output current for DQB. ASYMB read-write, 2 bits Asymmetry control. Controls asymmetry of VOL/VOH swing for DQB. |
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