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KM416RD8ACD-RK80 数据表(PDF) 55 Page - Samsung semiconductor |
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KM416RD8ACD-RK80 数据表(HTML) 55 Page - Samsung semiconductor |
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55 / 64 page  Page 52 KM416RD8AC(D)/KM418RD8AC(D) Direct RDRAM™ Rev. 1.01 Oct. 1999 CMOS - Transmit Timing Figure 58 is a timing diagram which shows the detailed requirements for the CMOS output signals. The SIO0 signal is driven once per tCYCLE1 interval on the falling edge. The clock-to-output window is tQ1,MIN/tQ1,MAX. The SCK and SIO0 timing points are measured at the 50% level. The rise and fall times of SIO0 are tQR1 and tQF1, measured at the 20% and 80% levels. Figure 58: CMOS Timing - Data Signals for Transmit VIH,CMOS 50% VIL,CMOS 80% 20% SCK SIO0 tQR1 tQF1 VOH,CMOS 50% VOL,CMOS 80% 20% tQ1,MAX VIH,CMOS 50% VIL,CMOS 80% 20% tHR,MIN VOH,CMOS 50% VOL,CMOS 80% 20% SIO0 tDR1 tDF1 tQR1 tQF1 tPROP1,MAX tPROP1,MIN or SIO1 SIO1 or SIO0 |
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