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KM416RD8ACD-RK80 数据表(PDF) 16 Page - Samsung semiconductor

部件名 KM416RD8ACD-RK80
功能描述  128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
PDF  64 Pages
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制造商  SAMSUNG [Samsung semiconductor]
网页  http://www.samsung.com/Products/Semiconductor
标志 SAMSUNG - Samsung semiconductor

KM416RD8ACD-RK80 数据表(HTML) 16 Page - Samsung semiconductor

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Page 13
KM416RD8AC(D)/KM418RD8AC(D)
Direct RDRAM
Rev. 1.01 Oct. 1999
ROW-to-ROW Interaction - contin-
ued
Cases RR13 through RR16 summarize the combinations of
two successive PRER commands. In case RR13 there is no
restriction since two devices are addressed. In RR14, tPP
applies, since the same device is addressed. In RR15 and
RR16, the same bank or an adjacent bank may be given
repeated PRER commands with only the tPP restriction.
Two adjacent banks can’t be activate simultaneously. A
precharge command to one bank will thus affect the state of
the adjacent banks (and sense amps). If bank Ba is activate
and a PRER is directed to Ba, then bank Ba will be
precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If
bank Ba+1 is activate and a PRER is directed to Ba, then
bank Ba+1 will be precharged along with sense amps
Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a
PRER is directed to Ba, then bank Ba-1 will be precharged
along with sense amps Ba/Ba-1 and Ba-1/Ba-2.
A ROW packet may contain commands other than ACT or
PRER. The REFA and REFP commands are equivalent to
ACT and PRER for interaction analysis purposes. The inter-
action rules of the NAPR, NAPRC, PDNR, RLXR, ATTN,
TCAL, and TCEN commands are discussed in later sections
(see Table 7 for cross-ref).
ROW-to-COL Packet Interaction
Figure 7 shows two packets on the ROW and COL pins.
They must be separated by an interval tRCDELAY which
depends upon the packet contents. Table 11 summarizes the
tRCDELAY values for all possible cases. Note that if the COL
packet is earlier than the ROW packet, it is considered a
COL-to-ROW packet interaction.
Cases RC1 through RC5 summarize the rules when the
ROW packet has an ACT command. Figure 15 and
Figure 16 show examples of RC5 - an activation followed by
a read or write. RC4 is an illegal situation, since a read or
write of a precharged banks is being attempted (remember
that for a bank to be activated, adjacent banks must be
precharged). In cases RC1, RC2, and RC3, there is no inter-
action of the ROW and COL packets.
Cases RC6 through RC8 summarize the rules when the
ROW packet has a PRER command. There is either no inter-
action (RC6 through RC9) or an illegal situation with a read
or write of a precharged bank (RC9).
The COL pins can also schedule a precharge operation with
a RDA, WRA, or PREC command in a COLC packet or a
PREX command in a COLX packet. The constraints of these
precharge operations may be converted to equivalent PRER
command constraints using the rules summarized in
Figure 14.
Figure 7: ROW-to-COL Packet Interaction- Timing
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T0
T4
T8
T12
T1
T5
T9
T13
T2
T6
T10
T14
T3
T7
T11
T15 T16
T
T17 T18 T19
Transaction a: ROPa
Transaction b: COPb
a0 = {Da,Ba,Ra}
b1= {Db,Bb,Cb1}
tRCDELAY
ROPa a0
COPb b1
Table 11: ROW-to-COL Packet Interaction - Rules
Case #
ROPa
Da
Ba
Ra
COPb
Db
Bb
Cb1
tRCDELAY
Example
RC1
ACT
Da
Ba
Ra
NOCOP,RD,retire
/= Da
xxxx
x..x
0
RC2
ACT
Da
Ba
Ra
NOCOP
== Da
xxxx
x..x
0
RC3
ACT
Da
Ba
Ra
RD,retire
== Da
/= {Ba,Ba+1,Ba-1}
x..x
0
RC4
ACT
Da
Ba
Ra
RD,retire
== Da
== {Ba+1,Ba-1}
x..x
Illegal
RC5
ACT
Da
Ba
Ra
RD,retire
== Da
== Ba
x..x
tRCD
Figure 15
RC6
PRER
Da
Ba
Ra
NOCOP,RD,retire
/= Da
xxxx
x..x
0
RC7
PRER
Da
Ba
Ra
NOCOP
== Da
xxxx
x..x
0
RC8
PRER
Da
Ba
Ra
RD,retire
== Da
/= {Ba,Ba+1,Ba-1}
x..x
0
RC9
PRER
Da
Ba
Ra
RD,retire
== Da
== {Ba+1,Ba-1}
x..x
Illegal



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