| 数据搜索系统,热门电子元器件搜索 |
|
KM416RD8ACD-RK80 数据表(PDF) 38 Page - Samsung semiconductor |
|
|
|||||||||||||||||||||||||||||
KM416RD8ACD-RK80 数据表(HTML) 38 Page - Samsung semiconductor |
|
38 / 64 page ![]() Page 35 KM416RD8AC(D)/KM418RD8AC(D) Direct RDRAM™ Rev. 1.01 Oct. 1999 . Figure 36: NAPX Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 DQS NAPX4..0 NAPXA4..0 Control Register: NAPX Address: 04516 Read/write register. Reset value is undefined Note - tSCYCLE is tCYCLE1 (SCK cycle time). NAPXA4..0 - Nap Exit Phase A. This field specifies the number of SCK cycles during the first phase for exiting NAP mode. It must satisfy: NAPXA•t SCYCLE ≥ tNAPXA,MAX Do not set this field to zero. NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK cycles during the first plus second phases for exiting NAP mode. It must satisfy: NAPX•t SCYCLE ≥ NAPXA•t SCYCLE+tNAPXB,MAX Do not set this field to zero. DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5 cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device selection on DQ5..0. See Figure 48 - This field must be written with a ″1″ for this RDRAM. Figure 37: PDNXA Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 PDNXA12..0 Read/write register. Reset value is undefined PDNXA4..0 - PDN Exit Phase A. This field specifies the number of (64•SCK cycle) units during the first phase for exiting PDN mode. It must satisfy: PDNXA•64•t SCYCLE ≥ tPDNXA,MAX Do not set this field to zero. Note - only PDNXA5..0 are implemented. Note - tSCYCLE is tCYCLE1 (SCK cycle time). Control Register: PDNXA Address: 04616 Figure 38: PDNX Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 PDNX12..0 Read/write register. Reset value is undefined PDNX4..0 - PDN Exit Phase A plus B. This field spec- ifies the number of (256•SCK cycle) units during the first plus second phases for exiting PDN mode. It must satisfy: PDNX•256•t SCYCLE ≥ PDNXA•64•t SCYCLE+ tPDNXB,MAX If this equation can’t be satisfied, then the maximum PDNX value should be written, and the tS4/tH4 timing window will be modified (see Figure 49) Do not set this field to zero. Note - only PDNX2..0 are implemented. Note - tSCYCLE is tCYCLE1 (SCK cycle time). Control Register: PDNX Address: 04716 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |