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MSC8152SVT1000B 数据表(PDF) 26 Page - Freescale Semiconductor, Inc |
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MSC8152SVT1000B 数据表(HTML) 26 Page - Freescale Semiconductor, Inc |
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26 / 68 page ![]() MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 1 Electrical Characteristics Freescale Semiconductor 26 2.5 DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8152. 2.5.1 DDR SDRAM DC Electrical Characteristics This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8152. Note: DDR2 SDRAM uses VDDDDR(typ) = 1.8 V and DDR3 SDRAM uses VDDDDR(typ) = 1.5 V. 2.5.1.1 DDR2 (1.8 V) SDRAM DC Electrical Characteristics Table 6 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR2 SDRAM. Note: At recommended operating conditions (see Table 3) with VDDDDR =1.8 V. Table 6. DDR2 SDRAM Interface DC Electrical Characteristics Parameter/Condition Symbol Min Max Unit Notes I/O reference voltage MVREF 0.49 × VDDDDR 0.51 × VDDDDR V2, 3, 4 Input high voltage VIH MVREF + 0.125 VDDDDR +0.3 V 5 Input low voltage VIL –0.3 MVREF – 0.125 V 5 I/O leakage current IOZ –50 50 μA6 Output high current (VOUT (VOH) = 1.37 V) IOH –13.4 — mA 7 Output low current (VOUT (VOL) = 0.33 V) IOL 13.4 — mA 7 Notes: 1. VDDDDR is expected to be within 50 mV of the DRAM VDD supply voltage at all times. The DRAM and memory controller can use the same or different sources. 2. MVREF is expected to be equal to 0.5 × VDDDDR and to track VDDDDR DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF with a minimum value of MVREF – 0.4 and a maximum value of MVREF + 0.04 V. VTT should track variations in the DC-level of MVREF. 4. The voltage regulator for MVREF must be able to supply up to 300 μA. 5. Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models. 6. Output leakage is measured with all outputs are disabled, 0 V ≤ V OUT ≤ V DDDDR. 7. Refer to the IBIS model for the complete output IV curve characteristics. |
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