MSC8152SVT1000B datasheet(3/68 Pages) FREESCALE

3 / 68 page

MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 1

Freescale Semiconductor

Figure 1. MSC8152 Block Diagram

Figure 2. StarCore SC3850 DSP Subsystem Block Diagram

JTAG

RMU

Note: The arrow direction indicates master or slave.

DDR Interface 64/32-bit

I/O-Interrupt

Concentrator

UART

Clocks

Timers

Reset

Semaphores

Other

DDR

CLASS

High-Speed Serial Interface

Modules

QUICCEngine

Four TDMs 256-Channels each

x1/x2/x4 3.125 Gbaud

Boot ROM

I2C

Virtual

Interrupts

Controller

SPI

DMA

Serial

DMA

Serial

MAPLE-B

x1/x4 3.125 Gbaud

Two DSP Cores at 1 GHz

Turbo/

SGMII

Viterbi

FFT/

IFFT

DFT/

IDFT

Two SGMII

RGMII RGMII

M3 Memory

1056 Kbyte

PCI-EX 1x/2x/4x

Subsystem

Dual RISC Processors

Ethernet

SPI

SC3850

DSP Core

512 Kbyte

32 Kbyte 32 Kbyte

ICache

DCache

L2 Cache / M2 Memory

RapidIO RapidIO

DDR Interface 64/32-bit

DDR

Controller

PCI

Expr

SerDes 1

SerDes 2

Two SGMII

32 Kbyte

Address

Translation

Task

Protection

32 Kbyte

(WTB)

(WBB)

EPIC

Interrupts

P-bus 128 bit

Xa-bus 64 bit

Xb-bus 64-bit

DQBus

Debug Support

OCE30

512 Kbyte L2 Cache / M2 Memory

MMU

Timer

128 bits master

IQBus

DPU

SC3850

Core

TWB

Write-

Through

Buffer

Write-

Back

Buffer

Instruction

Cache

Data

Cache

bus to CLASS

128 bits slave

bus from CLASS

MSC8152SVT1000B 数据表(PDF) 3 Page - Freescale Semiconductor, Inc

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