MSC8152SVT1000B datasheet(30/68 Pages) FREESCALE

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MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 1

Electrical Characteristics

Freescale Semiconductor

2.5.2.2

SerDes Reference Clock Receiver Characteristics

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding

SerDes lanes. The SerDes reference clock inputs are SR1_REF_CLK/SR1_REF_CLK or SR2_REF_CLK/SR2_REF_CLK.

Figure 5 shows a receiver reference diagram of the SerDes reference clocks.

The characteristics of the clock signals are as follows:

•

The supply voltage requirements for VDDSXC are as specified in Table 3.

•

The SerDes reference clock receiver reference circuit structure is as follows:

—The SR[1–2]_REF_CLK and SR[1–2]_REF_CLK are internally AC-coupled differential inputs as shown in

Figure 5. Each differential clock input (SR[1–2]_REF_CLK or SR[1–2]_REF_CLK) has on-chip 50-

termination to GNDSXC followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and

single-ended mode descriptions below for detailed requirements.

•

The maximum average current requirement also determines the common mode voltage range.

— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the

maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage

is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input

is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V

/ 50 = 8 mA)

while the minimum common mode input level is 0.1 V above GNDSXC. For example, a clock with a 50/50 duty

cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V),

such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode

voltage at 400 mV.

— If the device driving the SR[1–2]_REF_CLK and SR[1–2]_REF_CLK inputs cannot drive 50

Ω to GND

SXC DC or

the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled

externally.

•

The input amplitude requirement is described in detail in the following sections.

Figure 5. Receiver of SerDes Reference Clocks

Input

Amp

SR[1–2]_REF_CLK

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