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MSC8152SVT1000B 数据表(PDF) 49 Page - Freescale Semiconductor, Inc

部件名 MSC8152SVT1000B
功能描述  Dual-Core Digital Signal Processor
PDF  68 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MSC8152SVT1000B 数据表(HTML) 49 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
49
Table 35 presents the RGMII AC timing specification for applications required non-delayed clock on board.
Figure 25 shows the RGMII AC timing and multiplexing diagrams.
2.6.6
SPI Timing
Table 36 lists the SPI input and output AC timing specifications.
Table 35. RGMII at 1 GHz2 with No On-Board Delay3 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)4
tSKEWT
–2,6
–1.0
ns
Data to clock input skew (at receiver)4
tSKEWR
–0.5
0.5
ns
Notes:
1.
At recommended operating conditions with VDDIO of 2.5 V ± 5%.
2.
RGMII at 100 MHz support is guaranteed by design.
3.
GCR4 should be programmed as 0x000CC330.
4.
This implies that PC board design requires clocks to be routed with no additional trace delay
Figure 25. RGMII AC Timing and Multiplexing
Table 36. SPI AC Timing Specifications
Parameter
Symbol 1
Min
Max
Unit
Note
SPI outputs valid—Master mode (internal clock) delay
tNIKHOV
—6
ns
2
SPI outputs hold—Master mode (internal clock) delay
tNIKHOX
0.5
ns
2
SPI outputs valid—Slave mode (external clock) delay
tNEKHOV
—12
ns
2
SPI outputs hold—Slave mode (external clock) delay
tNEKHOX
2—
ns
2
SPI inputs—Master mode (internal clock) input setup time
tNIIVKH
12
ns
GTX_CLK
tSKEWT
TX_CTL
txd[7:4]
txd[3:0]
(At Transmitter)
TXD[3:0]
RX_CTL
rxd[8:5]
rxd[3:0]
RXD[3:0]
RX_CLK
(At Receiver)
tSKEWR



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