| 数据搜索系统,热门电子元器件搜索 |
|
MSC8152SVT1000B 数据表(PDF) 31 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MSC8152SVT1000B 数据表(HTML) 31 Page - Freescale Semiconductor, Inc |
|
31 / 68 page ![]() Electrical Characteristics MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 31 2.5.2.3 SerDes Transmitter and Receiver Reference Circuits Figure 6 shows the reference circuits for SerDes data lane transmitter and receiver. 2.5.3 DC-Level Requirements for SerDes Interfaces The following subsections define the DC-level requirements for the SerDes reference clocks, the PCI Express data lines, the Serial RapidIO data lines, and the SGMII data lines. 2.5.3.1 DC-Level Requirements for SerDes Reference Clocks The DC-level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs, as described below: • Differential Mode — The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection. — For an external DC-coupled connection, the maximum average current requirements sets the requirement for average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 7 shows the SerDes reference clock input requirement for DC-coupled connection scheme. Figure 6. SerDes Transmitter and Receiver Reference Circuits Figure 7. Differential Reference Clock Input DC Requirements (External DC-Coupled) 50 Ω 50 Ω 50 Ω 50 Ω Transmitter Receiver SR[1–2]_TXm SR[1–2]_RXm SR[1–2]_TXm SR[1–2]_RXm Note: The [1–2] indicates the specific SerDes Interface (1 or 2) and the m indicates the specific channel within that interface (0,1,2,3). Actual signals are assigned by the HRCW assignments at reset (see Chapter 5, Reset in the reference manual for details) SR[1–2]_REF_CLK SR[1–2]_REF_CLK Vmax < 800 mV Vmin > 0V 100 mV < Vcm < 400 mV 200 mV < Input Amplitude or Differential Peak < 800 mV |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |