ADP1048ARQZ-R7 datasheet(30/84 Pages) AD

30 / 84 page

ADP1047/ADP1048

Data Sheet

Rev. 0 | Page 30 of 84

ADVANCED FEATURES

The advanced features of the ADP1047/ADP1048 include

•

Frequency dithering for EMI noise minimization

•

PWM frequency synchronization with external source

•

Smart output voltage: real-time efficiency optimization by

changing the output voltage based on ac line and output power

•

Smart switching frequency: real-time efficiency

optimization by changing the switching frequency

•

Current loop filter for light load: real-time THD

optimization at light load conditions

•

Phase shedding (ADP1048 only): real-time efficiency

optimization by shutting down one phase

•

Current loop feedforward: power factor and THD

optimization at light load conditions

•

Bridgeless boost operation (ADP1048 only)

All advanced features other than bridgeless boost operation are

enabled by setting the appropriate bit in Register 0xFE4F.

FREQUENCY DITHERING (SPREAD SPECTRUM)

The PWM signal can be altered digitally to optimize for EMI

reduction (see Figure 28). For a wider but lower EMI spectrum,

the switching frequency varies with the rectified line voltage.

The switching cycle changes linearly with time from 87.5% to

112.5% of the nominal value, resulting in a frequency variation

of 114% to 89% of the nominal value.

To enable frequency dithering, set Register 0xFE4F, Bit 0, to 1.

To configure the dithering period, program Register 0xFE1D.

TIME

1/f DITHER

2/f DITHER

TIME

SWITCHING

CYCLE

SWITCHING

FREQUENCY

VREC

112.5% tSW

tSW

87.5% tSW

114% fSW

fSW

89% fSW

Figure 28. Switching Frequency Dithering Control

PWM FREQUENCY SYNCHRONIZATION

The part can synchronize the internal PWM clock with an

external clock frequency; the external source must be within the

minimum and maximum synchronization range programmed

in the part. To enable PWM frequency synchronization, set

The capture range for the SYNC period is 87.5% to 112.5% of

the programmed switching period. The switching frequency

synchronized to the SYNC pin is limited by the frequency set

in Register 0xFE1B. The maximum range for the synchronized

frequency is from 89% to 114% of the programmed switching

frequency. The delay between the external SYNC signal and the

start of the internal switching cycle can be programmed using

The part synchronizes to the external clock frequency as follows:

The part attempts to determine the external clock period,

averaging it over seven cycles (frequency capture mode).

After the period of the SYNC signal is determined, the

internal PWM clock is adjusted until the phase is also

aligned. At that point, internal and external clocks are

synchronized (phase capture mode).

Each internal switching cycle is terminated after the SYNC

rising edge is detected (pulse-by-pulse synchronization).

If the external SYNC signal is lost at any time or if the period

exceeds the minimum/maximum limit, the internal clock goes

back to the maximum period set in Register 0xFE1B.

During the soft start phase, the SYNC pin is ignored and the

clock frequency is not synchronized.

Interleaved operation of a multiphase PFC circuit is realized by

using the SYNC pin of several ADP1047/ADP1048 controllers.

The frequency synchronization feature is optional. When

enabled, the switching frequency can be programmed to 1,

1/2, 1/3, or 1/4 of the SYNC frequency using Register 0xFE1E.

SMART OUTPUT VOLTAGE (LOAD LINE)

To achieve higher efficiency, the output voltage can be

programmed according to the load power and input voltage

condition (see Figure 29). To enable the smart output voltage

feature, set Register 0xFE4F, Bit 2, to 1.

SUPER HIGH LINE

POWER

VOH

VOH2

VOH1

VOL2

VOL1

100%

OUTPUT

VOLTAGE

HIGH LINE

LOW LINE

Figure 29. Smart Output Voltage Control (Load Line)

ADP1048ARQZ-R7 数据表(PDF) 30 Page - Analog Devices

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