ADP1048ARQZ-R7 datasheet(68/84 Pages) AD

68 / 84 page

ADP1047/ADP1048

Data Sheet

Rev. 0 | Page 68 of 84

FREQUENCY SYNCHRONIZATION SET REGISTER

Table 92. Register 0xFE1E—Frequency Synchronization Set

Bits

Bit Name

R/W

Description

[7:2]

RSVD

R/W

Reserved.

[1:0]

Frequency division

R/W

Sets the frequency division between the switching frequency and the external SYNC clock

(fSW/fSYNC_EXT).

Bit 1

Bit 0

Frequency Division

1/2

1/3

1/4

VOLTAGE LOOP FILTER GAIN REGISTER

Table 93. Register 0xFE20—Voltage Loop Filter Gain

Bits

Bit Name

R/W

Description

[7:0]

Voltage loop filter

gain

R/W

Determines the digital filter gain of the PFC voltage loop.

VOLTAGE LOOP FILTER ZERO REGISTER

Table 94. Register 0xFE21—Voltage Loop Filter Zero

Bits

Bit Name

R/W

Description

[7:0]

Voltage loop filter

zero

R/W

Determines the position of the digital filter zero of the PFC voltage loop.

FAST VOLTAGE LOOP FILTER GAIN REGISTER

Table 95. Register 0xFE22—Fast Voltage Loop Filter Gain

Bits

Bit Name

R/W

Description

[7:0]

Fast voltage loop

filter gain

R/W

Determines the digital filter gain of the PFC fast voltage loop.

FAST VOLTAGE LOOP FILTER ZERO REGISTER

Table 96. Register 0xFE23—Fast Voltage Loop Filter Zero

Bits

Bit Name

R/W

Description

[7:0]

Fast voltage loop

filter zero

R/W

Determines the position of the digital filter zero of the PFC fast voltage loop.

FAST VOLTAGE LOOP ENABLE REGISTER

Table 97. Register 0xFE24—Fast Voltage Loop Enable

Bits

Bit Name

R/W

Description

Enable fast loop

for line transient

R/W

Enables fast loop mode immediately after the overshoot becomes larger than the regulation band

plus 3%.

1 = enable fast loop mode.

0 = disable fast loop mode.

[6:5]

Regulation band

limit

R/W

Sets the threshold of the regulation band limit for switching from the normal filter to the fast loop

filter.

Bit 6

Bit 5

Threshold

±1.5625%

±3.125%

±6.25%

±12.5%

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