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ADP1048ARQZ-R7 数据表(PDF) 58 Page - Analog Devices

部件名 ADP1048ARQZ-R7
功能描述  Digital Power Factor Correction Controller
PDF  84 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1048ARQZ-R7 数据表(HTML) 58 Page - Analog Devices

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ADP1047/ADP1048
Data Sheet
Rev. 0 | Page 58 of 84
CS_FAST_OCP_RESPONSE REGISTER
This register instructs the device on actions to take due to a fast overcurrent protection condition.
Table 62. Register 0xFE00—CS_FAST_OCP_RESPONSE
Bits
Bit Name
R/W
Description
[7:6]
Response
R/W
These bits determine the device response to a fast overcurrent protection condition.
Bit 7
Bit 6
Response
0
0
Ignore (still terminate the PWM pulse).
0
1
Allow the number of switching cycles specified in Bits[5:4], then shut down and
soft start (use the soft start delay time specified in Register 0x5C, Bits[2:0]).
1
0
Allow the number of switching cycles specified in Bits[5:4] (terminating the PWM
pulse each time), then shut down and wait for the PSON signal to soft start.
1
1
Disable the PWM output after the number of switching cycles specified in Bits[5:4]
and wait for the flag to be cleared.
[5:4]
N-time
R/W
These bits determine the number of switching cycles allowed before the device disables the PWM
output after a fast overcurrent condition is detected.
Bit 5
Bit 4
Number of Switching Cycles
0
0
1
0
1
2
1
0
4
1
1
8
[3:0]
RSVD
R
Reserved.
OVP_FAST_OVP_RESPONSE REGISTER
This register instructs the device on actions to take due to a fast overvoltage fault condition.
Table 63. Register 0xFE01—OVP_FAST_OVP_RESPONSE
Bits
Bit Name
R/W
Description
[7:6]
Response
R/W
These bits determine the device response to a fast overvoltage condition.
Bit 7
Bit 6
Response
0
0
Ignore (do nothing; PWM continues).
0
1
Shut down and soft start.
1
0
Shut down immediately and wait for the PSON signal.
1
1
Disable the PWM output until the unlatched flag is cleared.
[5:0]
RSVD
R
Reserved.
OLP_RESPONSE REGISTER
This register instructs the device on actions to take due to an open-loop fault condition.
Table 64. Register 0xFE02—OLP_RESPONSE
Bits
Bit Name
R/W
Description
[7:6]
Response
R/W
These bits determine the device response to an open-loop fault condition.
Bit 7
Bit 6
Response
0
0
Ignore (do nothing; PWM continues).
0
1
Shut down and soft start.
1
0
Shut down immediately and wait for the PSON signal.
1
1
Disable the PWM output until the unlatched flag is cleared.
[5:0]
RSVD
R
Reserved.



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