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ADP1048ARQZ-R7 数据表(PDF) 80 Page - Analog Devices |
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ADP1048ARQZ-R7 数据表(HTML) 80 Page - Analog Devices |
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80 / 84 page  ADP1047/ADP1048 Data Sheet Rev. 0 | Page 80 of 84 POWER METERING GAIN TRIM FOR HIGH LINE INPUT REGISTER Table 154. Register 0xFE8F—Power Metering Gain Trim for High Line Input Bits Bit Name R/W Description 7 Gain trim polarity R/W 1 = negative gain trim is introduced. 0 = positive gain trim is introduced. [6:0] Power meter gain trim R/W This value calibrates the power meter gain at the high line input voltage. Each LSB corresponds to 0.0625/128 of the input power. CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT AND LIGHT LOAD REGISTER Table 155. Register 0xFE90—Current Loop Filter Gain for Low Line Input and Light Load Bits Bit Name R/W Description [7:0] Current loop filter gain for low line and light load R/W These bits set the current loop digital filter gain of the PFC current loop under the low line input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. CURRENT LOOP FILTER ZERO FOR LOW LINE INPUT AND LIGHT LOAD REGISTER Table 156. Register 0xFE91—Current Loop Filter Zero for Low Line Input and Light Load Bits Bit Name R/W Description [7:0] Current loop filter zero for low line and light load R/W These bits set the current loop digital filter zero of the PFC current loop under the low line input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. CURRENT LOOP FILTER GAIN FOR HIGH LINE INPUT AND LIGHT LOAD REGISTER Table 157. Register 0xFE92—Current Loop Filter Gain for High Line Input and Light Load Bits Bit Name R/W Description [7:0] Current loop filter gain for high line and light load R/W These bits set the current loop digital filter gain of the PFC current loop under the high line input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. CURRENT LOOP FILTER ZERO FOR HIGH LINE INPUT AND LIGHT LOAD REGISTER Table 158. Register 0xFE93—Current Loop Filter Zero for High Line Input and Light Load Bits Bit Name R/W Description [7:0] Current loop filter zero for high line and light load R/W These bits set the current loop digital filter zero of the PFC current loop under the high line input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. SMART VOUT POWER READING REGISTER Table 159. Register 0xFE94—Smart VOUT Power Reading Bits Bit Name R/W Description [15:0] Power reading R Return the average power reading for smart output voltage (averaged over 16 full line cycles). |
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